OUTLOOK 2018 – RISC-V could revolutionise the embedded systems market

Today, just as many market-leading technology offerings have been developed on the base of open communities as those from traditional R&D – and the opportunities to leverage open platforms in combination with a company’s differentiated competencies and market insight often result in inspired roadmaps that can be put on a fast track.

Today, open-source software and the innovation that streams from it interacts routinely with our daily lives – most would say for the better. For example, the Linux operating system powers millions of servers driving internet commerce, applications and databases. And it’s only 10 years since the Open Handset Alliance introduced the Android open-source mobile phone platform and its adoption by manufacturers and developers has swelled globally. While Google offers the source code through an open-source license, the innovative apps and services that reach Android-powered mobile phones and tablets are, ultimately, a combination of the (free) open-source software and layers of proprietary code delivered by the community of developers and OEMs.

The logical next step for Android? The Internet of Things. It would be hard to discount the potential of the Android Things platform when considering the army of loyal developers, which stands to benefit greatly from emerging markets for wearables, automotive applications and industrial solutions (to name just a few).

It is unlikely the earliest prophets of open-source software could have predicted a parallel movement towards open hardware, but it is here in a variety of formats – from Raspberry Pi to Arduino to Beaglebone. And the open philosophy is about to move further into the embedded world with a swelling community of RISC-V supporters, envisioning a familiar and fast-maturing set of benefits within their grasp.

Originally developed at the University of California, Berkeley, RISC-V is an open instruction set architecture (ISA) that is freely available to academic institutions and corporations. It was conceived with the implicit outcome of not being over-architected, while still being a fully-virtualisable ISA ready for direct hardware implementation. Today, it offers 32bit, 64bit and 128bit address space variants for applications, operating system kernels and hardware implementations.

The RISC-V Foundation’s goal is ‘to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites and teaching materials’.

While it’s not likely that market-leading ‘closed’ processor architectures will be any less important in designers’ minds, the RISC-V processor ecosystem is poised for rapid growth in the embedded market. The ISA’s ‘inspectable’, open nature is just one of the intriguing elements awaiting design engineers as they take a closer look at this technology’s features.

Stability: New design development with RISC-V is straightforward, with a standard base set of less than 50 instructions and multiple standard extensions. Since the base user spec has been frozen, additions to the standard instruction set will be made through extensions, not through new ISA versions, meaning investments in software will be preserved. Software written for a RISC-V core will run on any equivalent device forever. The standard instructions and extensions serve to provision a high level of stability for future design. And with a modest quantity of instructions, simple architectures can be created, which leads to cost-effective and power-efficient processors.

Portability: RISC-V leverages the open nature of community-based architectures, meaning that software is portable across all devices with a RISC-V core. With this ‘royalty-free’ processor sub-system and register-transfer level (RTL) code implemented in hardware, engineers can migrate, adapt and modify their designs to their chosen product platform. Unlike standard x86 or ARM processor approaches, teams could conceivably bring a new product to market in an FPGA featuring a soft-gate version of the RISC-V core. When volume dictates, designers can retarget the RTL source to an ASIC without consideration for royalty fees.

Security: Engineers understand the value of working directly with RTL source code – the model upon which logical operations impact digital signals as they link to various hardware registers within a digital circuit. RISC-V designers will have clear visibility of the underlying RTL source code – a boost for trust and security. Booting a RISC-V core from secure flash on a chip offers the opportunity to confirm secure operation at that stage and we are already seeing this level of security implemented by first movers among the RISC-V community. This bodes well for companies that will have a role in tomorrow’s most promising (and secure) RISC-V based innovations.

Flexibility: The RISC-V approach will be an impactful catalyst for a diverse group of solutions. A RISC-V designer will be able to build a system with multiple, functionally-equivalent cores, enabling high redundancy due to their autonomous design. One core might be a Microsemi core, another other could be a functionally-equivalent in-house design. By offering complete flexibility over the micro-architecture, RISC-V adopters will be able to deliver single event upset protective measures for data and instruction cache memory. In markets where safety and security-conscious applications are at a premium, RISC-V designs will be an attractive alternative.

Community: The RISC-V instruction set architecture is covered under a permissive Berkeley software distribution license, so we should expect that designers will recognise its value and establish new strategies to deploy within their roadmaps. As adoption increases, more engineers will seek to leverage the open-source community and collectively address today’s design challenges, resulting in new ways of thinking about what is possible. It’s not hard to imagine engineers working together to migrate, modify and adapt designs to a particular hardware platform discovering new levels of productivity and innovation. Proven hardware acceleration approaches could be used to achieve high-performance solutions for any number of design challenges.

Momentum: With an open exchange of ideas and a history of practical success from the world of open-source software, there is plenty of optimism that microcontrollers and embedded processors will be the next beneficiaries of collaboration, enabling participants to layer their own high-value proprietary IP on a well-understood foundation.

The emergence of open-hardware workshops, the proliferation of RISC-V topics in development conferences and the emergence of the RISC-V Foundation itself, with a growing roster of members, all point to a dynamic development future. We should expect smaller companies and research universities, which have not until now had the means, to play a direct role in chip design. We should expect to see larger organisations to continue to package their market-ready IP with the RISC-V ISA. And we should expect to see innovative development boards giving rise to compelling new applications from the ‘maker’ community mindset.

The RISC-V ISA opens great opportunities in computer architecture and it may be as close as we can get to mainstream open hardware in a corporate setting. The promise of rapid prototyping, new ideas from new and established industry participants and collaborative advancements among industry leaders are setting the stage for a provocative (near) future.