Clock buffer targets 4G LTE wireless infrastructure systems
Mixed signal and analogue specialist IDT has introduced a new clock fanout buffer that supports high speed JESD204B clocking.
The low noise 8V79S690i is a two channel clock and SYSREF fanout buffer with configurable phase delay and ultra low additive phase noise.
Supporting frequencies such as 614.4 and 1228.8MHz, the device addresses the latest generation of high speed a/d and d/a data converters, delivering high quality, synchronous clock and SYSREF signals to improve overall base station signal quality and increase data throughput via lower system bit error rates.
Furthermore, IDT says base station developers can reduce system costs by simplifying filters as a result of less noise in the signal path.
