Engineering publications brought to you by Mark Allen

Risc v

Embedded Studio for RISC-V now comes with SEGGER Linker

Green Hills adds RTOS support to portfolio of RISC-V-based SoCs

Silicon Labs selects Imperas RISC-V Reference Model for verification

Codasip announces RISC-V processor cores providing multi-core and SIMD capabilities

Imperas extends free riscvOVPsimPlus simulator for RISC-V

Andes announces new RISC-V processors

IAR Embedded Workbench for RISC-V extends optimisation and trace capabilities

Sundance launches RISC-V module to support embedded system development

IAR Systems brings functional safety tools to RISC-V

Renesas selects Andes RISC-V 32-Bit CPU cores

Codasip Whitepaper - Creating domain-specific processors using custom RISC-V ISA instructions

RISC-V embedded variant RV32E supported by SEGGER's floating-point library