It’s the Law

Research & Development in the semiconductor industry is dominated by one thing: the need to follow Moore’s Law. The consequence of this is the self imposed requirement to double the number of transistors on a given piece of silicon every 18 months whilst cutting cost along the way. Leaving aside the financial requirements, the technical challenges are getting ever more complex as researchers close in on the theoretical limits of scaling the cmos semiconductor manufacturing process. The last year or so has seen 65nm manufacturing become more common, along with early indications of progress towards 45nm – the next process node – and beyond to 32nm and 22nm. And it’s the 22nm node that, at the moment, appears to be the limit for cmos as we know it. Dealing with such minuscule dimensions has meant new approaches – not only in the physical structure of transistors themselves, but also in the way in which they are patterned on the base silicon wafer.