The missing link?

Functional testing is heavily relied upon for the testing of completed product firmware, but the development and execution of FTs can be the cause of many bottlenecks during product introductions. Furthermore, bought in third party FT cores often incur high IP licensing costs. However, through the judicious use of existing resources and a degree of ingenuity, engineers at Renishaw were able to extend the use of Jtag supported fpga access to internal built in self test (BIST) functions, also developed in house. Gloucestershire based Renishaw, which specialises in metrology and spectroscopy, has R&D, manufacturing, sales and service operations in more than 30 countries. Since the early 1990s, electronics has played a key role in the measurement and control functions of Renishaw's products – equipment that is acknowledged around the world as being amongst the foremost in the fields of coordinated measurement and machine tool automation. Understandably, as electronic systems evolved over the years, the test methods used to check them have needed to keep pace. For example, in the early 1990s, Renishaw could test almost everything on a pcb using in circuit test (ICT) machines and then perform a few basic FTs. However, large scale integration and the absorption of many [product] functions into fpgas meant new test strategies had to be adopted. True value As a metrology company, Renishaw already appreciated the value that inspection and test brings to the efficiency of an organisation; without the feedback that testing provides, manufacturing process faults cannot be corrected. Boundary scan testing of pcbs was first adopted by Renishaw in the early part of this decade. Specifically, following a stringent evaluation process, JTAG Technologies was selected as the system supplier – and the two companies have since worked closely to enhance and develop test solutions. Currently, JTAG Technologies supplies equipment for integration in Aeroflex ICT systems and in functional test stations, custom built using components from National Instruments and other vendors. A bespoke JTAG Technologies signal conditioning pod for the Aeroflex 42xx was launched last year. With a view to reducing the FT bottlenecks, Renishaw investigated the use of Jtag (re)programmable fpga cores to implement 'at speed' functional testing of peripheral circuits; and to then implement it into a production friendly package. The company had previously devised a method for accessing post configuration fpga logic, using a proprietary feature of Altera Cyclone devices known as the VJI (Virtual Jtag Interface) MegaFunction. The company had presented a paper at JTAG Technologies' 2007 User Day on the use of VJI to enhance flash memory programming performance. Adapting the VJI approach to support BIST functions was the next logical step and the first task was to produce reusable BIST cores for a/d and d/a converter circuits, which are accessed via an fpga. The first project to benefit from this technique was an Ethernet interface board for a machine tool probe. For this initial BIST exercise, the Vhdl design was subdivided into seven blocks – U1 to U7. U1 is effectively the gateway between Altera's VJI and the BIST logic itself. It provides an addressable system using a 16bit databus and a wide address bus. U2 is the PLL based clock source(s) for the a/d and d/a converter tests – for this application the clock speed is 33MHz. U3 is a small memory block that allows the user to read back revision codes for the BIST cores. U4 is a dual port ram that can be loaded from the internal bus structure via the VJI interface. The memory has the capacity to output 1k of 12bit resolution samples at the maximum a/d conversion rate of 33MHz. U5 formats output from the dual port ram for the parallel d/a converter. Waveform output is triggered by the VJI interface and can be single shot or continuous. U6 is a repeat of the dual port ram block, this time used to receive data as a result of the a/d converter tests. Up to 1k of 8bit resolution samples can be stored in this block. U7 parallelises the serial data from the a/d converter and writes it to the dual port ram. Triggering options such as signal level and polarity can be controlled by the VJI interface. Jtag aspects Of course, there is more than one way that such fpga resident test code could be loaded and executed, but most of these methods would involve the use of additional programming hardware, software and possibly more resources, such as fpga I/O pins. Using Jtag as both the BIST core programming mechanism and the control/ results retrieval channel provides several benefits for this FT extension, including: ? Reuse of tester hardware from 'conventional' Jtag testing, thus saving the cost of employing device specific access hardware ? Fast programming of BIST core (less than 3.5s) using high performance hardware from JTAG Technologies. (New .NET compatible routines were introduced in 2009, following a request from Renishaw) ? Routines are easily called and integrated into the existing TestStand application executive ? No need to assign specific fpga pins for control of BIST logic ? Fast data retrieval; 150ms to retrieve 1K d/a converter samples. This rate was achieved because the High Level Scan library (HSL) routines were compiled into C code, rather than existing as interpreted code. HSL routines, written in C, ease the integration of Jteg based testing and FTs. In addition, Renishaw wanted to take care of the integration into TestStand. Whilst the HSL routines are shipped in a DLL format, this particular set of applications for the BIST programming and activation needed to be built as a National Instruments' TestStand step type. Once this level of work was completed, the BIST functions could be loaded and executed seamlessly alongside existing 'standard' Jtag applications. In conclusion, Renishaw was able to achieve 'at speed' functional testing through linking Jtag supported fpga access to internal BIST functions. What's more, the resulting routines can be integrated into existing test plans, negating the need for any further training of sequence developers or operators.