With larger and more complex SoCs and disaggregated multi-chip systems being developed to accommodate escalating compute demands, data delivery within and between silicon components has become more challenging, impacting power, performance and area (PPA).
The Janus NoC has been developed to better manage simultaneous high-speed communications more efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.
“Cadence is an established leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services capabilities to enable our customers to develop differentiated and disaggregated designs,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “The addition of the Cadence Janus NoC to our growing system IP portfolio is a key milestone in this strategy. Our evolution from an IP provider to an SoC design partner delivers greater value to our customers, empowering them to focus valuable engineering resources on differentiating their silicon.”
The Janus NoC leverages Cadence’s Tensilica RTL generation tools and customers can utilisee Cadence’s extensive portfolio of software and hardware for simulation and emulation of their NoC and gain deepr insights into its performance using Cadence’s System Performance Analysis tool (SPA).
According to Cadence, the Janus NoC mitigates the routing congestion and timing issues associated with complex SoC interconnects, which often don’t become apparent until physical implementation. Cadence’s first-generation NoC provides a platform for future innovations, such as support for industry-standard memory and I/O coherence protocols.
Current features and benefits include:
- Easy to use: Cadence’s state-of-the-art GUI enables easy NoC configuration ranging from small subsystems to full SoCs and future multi-chip systems.
- Accelerated time to market: PPA-optimised RTL enables SoC designers to achieve their bandwidth and latency goals. Packetised messages enable higher utilisation of wires, reducing wire count and timing closure challenges.
- Lower risk: The NoC’s built-in power management, clock domain crossing and width matching reduce design complexity.
- Quick turnaround: Cadence’s extensive simulation and emulation capabilities enable early architectural exploration, allowing quick validation of PPA results to ensure the configuration meets design requirements.
- Scalable architecture: Customers can design a subsystem and reuse it in a full SoC context of the NoC, allowing future reuse in a multi-chip system.
- Flexible: The NoC is compatible with any IP with an industry-standard interface, including AXI4 and AHB.
“We are pleased that Cadence is expanding its IP portfolio by investing in system-level solutions,” said Suk Lee, VP and GM, Ecosystem Technology Office at Intel Foundry. “As a NoC is vital for almost any subsystem in today’s SoCs, we support Cadence’s initiatives in developing their NoC and look forward to them continuing to expand their IP offering going forward.”
