Graham Pitcher

FPGA IP core targeted at 16nm processes

News
1 min read

Flex Logix has completed the design of its second-generation IP core for use in devices to be made on TSMC’s 16FF+ and 16FFC processes. Enabling embedded FPGA arrays with more than 100,000 LUTs, the latest core allows chips to customised and upgraded in the field. This flexibility, says the company, will be key for those designing next generation networking, base station, data centre accelerator and deep learning chips, where changing standards, architectures and customer requirements require design flexibility.

“Data centres require reconfigurable hardware protocols for networking, storage and security. Therefore switches, NICs and other networking chips need high-performance reprogrammability,” said Geoff Tate, Flex Logix’ CEO. “The EFLX 2.5K embedded FPGA enables this ability in chips cost effectively and at high performance.”

The EFLX 2.5K core can be ‘arrayed’ to build embedded arrays ranging in size from 1x1 (2.5k LUTs) up to 7x7 (122.5k LUTs). Logic and DSP versions are available and both are said to be interchangeable. While the logic version is entirely programmable logic, the DSP version substitutes some LUTs for 40 MACs, each with a pre-adder, a 22 x 22bit multiplier and a 48bit accumulator.

The 16nm version of EFLX-2.5K features six input LUTs (that can also be dual five input LUTs), each with dual outputs and dual optional flip flops. MACs are pipelined 10 in a row to provide local interconnect for FIR filters, while a new test mode enables much faster test times. Requiring only six routing layers of metal, the core is said to be compatible with most metal stacks.

An EFLX-2.5K IP core produced using TSMC 16FF+/FFC is said to occupy 1mm2 of silicon.

FPGA core
embedded FPGA
IP core
http://www.flex-logix.com/