As an open instruction set architecture (ISA), RISC-V’s inherent configurability and efficiency mean that its able to provide a suitable foundation to drive innovation forward in critical sectors of the space computing landscape.
“Building on over 25 years of successfully using the SPARC open ISA in space, this effort is an important step forward in the transition to the emerging and equally open RISC-V architecture,” said Roland Weigand, Technical Officer at ESA. “RISC-V is the preferred architecture across a wide range of space products, from microcontrollers to advanced SoC-FPGAs and high-performance microprocessors for on-board data processing.”
For this project, Frontgrade Gaisler will be concentrating on deterministic operation and minimal latency so that the new RISC-V processor IP will execute tasks predictably and reliably and quickly respond to input stimuli.
With these additional benefits, the processor can be integrated into radiation-hardened microcontrollers and field-programmable gate arrays (FPGAs) that support space missions. This model will extend the RISC-V ecosystem and complement the NOEL-V RISC-V processor, which shares the focus on space applications with an emphasis on high-performance capabilities.
"Frontgrade Gaisler has decades of experience supplying the space industry with products that implement open standards, and now we’re applying our proven know-how to bring RISC-V advancements to the space industry," said Sandi Habinc, General Manager at Frontgrade Gaisler. “Our team is committed to providing tangible benefits that help progress and grow the entire space community and enable new types of space missions.”
