imec develops roadmap for 7nm and 5nm FinFETs

At the VLSI 2013 symposium in France, the research institute presented the first strained Germanium devices based on a Si replacement process, where a Ge/SiGe quantum well heterostructure is grown by epitaxially replacing a conventional Si based shallow trench isolation. The technique is said to allow for means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous FinFET/nanowire devices. Aaron Thean, programme director of logic devices at imec, commented: "We are facing significant challenges to scale the mosfet architecture towards 7nm and 5nm. "Besides dimension scaling, enhancing the device performance in the face of rising parasitics and power is a major focus of the logic device research at imec. Among the key activities are R&D efforts investigating both high mobility channel material and new methods of enhancing Si based FinFET." Also unveiled at VLSI 2013 was a novel, highly scalable engineering approach to tune gate work function and improve mobility, noise and reliability in Si nMOS FinFETs. Furthermore, imec presented simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics. The research, it says, will provide important process guidance to extend FinFET scalability.