The initial release is for RV32IMC, RV64 and other ratified extensions are under development and will also be released as part of the riscvOVPsimPlus, package with a free-to-use permissive license from Imperas, which covers free commercial as well as academic use.
Design Verification (DV) teams use coverage analysis as the key metric for progress towards completion of verification plans. In a complex design such as a RISC-V processor, the ISA (Instruction Set Architecture) provides the basic guidelines for instruction level functionality.
The development of an instruction level SystemVerilog functional coverage library requires both an understanding of the verification process and the general requirements of the DV community.
Imperas had previously developed these libraries over time to support multiple customer projects and users of the Imperas commercial tools, such as ImperasDV. However, with the rapid growth in RISC-V adoption and many new teams now undertaking a complex RISC-V processor DV task for the first time, the emerging RISC-V verification community has an urgent need for quality Verification IP from a reliable source.
SystemVerilog and UVM are said to be the most trusted standards in SoC and IP verification.
“Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture,” said Allen Baum of Esperanto Technologies, and Chair of the RISC-V International Architecture Test SIG. “The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.”
“The open standard ISA of RISC-V provides great flexibility for innovation in the design of modern processor implementations,” said Simon Davidmann, CEO at Imperas Software. “With all the configurability offered by the standard extensions and implementation options, plus users-defined custom features, the total scope of the RISC-V verification effort cannot be understated. Through our experience working with some of the most sophisticated customer designs we recognise the usefulness of ready-to-use SystemVerilog Verification IP that allows developers a solid foundation on which to build a successful DV plan.”
