As IC designs continue to grow in both size and complexity, engineers must identify and address testability issues at the earliest possible stages of design.
Siemens’ Tessent software looks to address this by enabling the analysis and insertion of a large majority of DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern generation) to identify and address outlier blocks and take appropriate measures.
Extending the Tessent portfolio’s design editing capabilities, Tessent RTL Pro automates the analysis and insertion of test points, wrapper cells, and x-bounding logic earlier in the design flow, which can help customers shorten design cycles and improve the testability of their designs. Unlike many competing solutions, Tessent RTL Pro is also able to handle complex Verilog and SystemVerilog constructs while maintaining the look and feel of the original RTL design.
Tessent RTL Pro enables analysis of RTL complexity and its adaptability for test point insertion, evaluating whether the customer’s RTL structure can be edited efficiently, which is a critical factor when adding test points throughout the design. This functionality can help customers reduce their design turn-around-time and improve time-to-market.
Tessent RTL Pro’s "shift-left" functionality also helps enhance the ability of third-party tools to optimise area and timing when adding DFT logic prior to synthesis, leaving only scan insertion for the gate level. Design insertion happens at the RTL development stage, with RTL output, allowing seamless integration with third-party synthesis and verification software. In addition, RTL Pro generates design files that work with any downstream synthesis or verification flows, without requiring a closed-flow process.
“Tessent RTL Pro continues Siemens’ drive to provide the industry’s most advanced solutions to chip designers and DFT engineers for their design flows,” said Ankur Gupta, vice president and general manager, Tessent division, Siemens Digital Industries Software. “With the ability to analyse and insert wrapper cells, x-bounding logic, and VersaPoint test points at the RTL stage of design, customers can now extend their shift-left initiatives by substantially enhancing the testability of their designs.”
