IP cores target dataplane and signal processing functions
Extending its portfolio of IP cores for compute intensive dataplane and dsp functions, Tensilica has announced the introduction of the Xtensa LX4 dpu for SoCs.
The device supports local data memory bandwidth up to 1024bits per cycle, VLIW instructions up to 128bits for increased parallel processing and a cache memory prefetch option designed to boost overall performance for systems with long off chip memory latency.
Applications include imaging, video, networking and baseband wired/wireless communications.
"With the addition of the Xtensa LX4, Tensilica offers IP cores that range from an ultra small programmable dpu as exemplified by a 1GigaMAC dsp in 0.01mm2 (in 28nm process technology) up to the ConnX BBE 64-128, the world's highest performance licensable dsp IP core with more than 100GigaMAC/s performance."
