Axiomise launches footprint, area analyser for silicon design

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Axiomise, a provider of formal verification solutions, has announced the launch of footprint, an area analyser solution designed to transform power, performance and area (PPA) optimisation for silicon design.

Aximose unveils footprint an area analyser for silicon design Credit: Andrei Armiagov - adobe.stock.com

PPA has become an even bigger challenge than it was previously, a result of larger AI/ML hardware designs. footprint, powered by the new Axiomiser platform, has been developed to discover redundant gates and registers in complex system on chips (SoCs) that consume power but are never used.

The solution finds component-level granularity to precisely identify which design components never get used while still consuming power. Synthesis solutions cannot always clean out the redundant area.

“footprint is a key step in realising our vision of making formal normal,” remarked Dr. Ashish Darbari, Founder and CEO of Axiomise. “It’s a powerful tool that provides architects and designers with a quick feedback loop during design bring-up, enabling them to exhaustively analyse silicon waste while optimising for power and performance.”

footprint comes with an agile, interactive and user-centric interface, that enables rapid model refinement and has been successfully tested on more than 80 designs, including processors, GPUs, communication IP, and NoCs. footprint works with any formal verification tool to generate clear, easy-to-read reports while surpassing traditional reachability and structural coverage analysis.