Such devices are said to offer simplified processing, improved reliability, reduced low frequency noise and lower IOFF values, making them attractive for advanced logic, low power circuits and analogue/RF applications. In particular, GAA-NWFETs are believed to be a promising candidate for scaling CMOS processes beyond the 5nm node.
“Imec’s work has contributed to an increased and more in depth understanding of junctionless GAA-NWFETs,” stated Dan Mocuta, director of logic device and integration at imec. “Our thorough evaluation highlighted the excellent performance of junctionless lateral and vertical nanowire devices for beyond 5nm logic devices. Moreover, junctionless devices appeared as a viable option for analogue/RF applications, whereas stacked junctionless vertical NWFETs could reduce SRAM area significantly.”
By taking advantage of the process simplicity of junctionless devices, imec proposed an SRAM cell design with two vertically stacked junctionless vertical NWFETs with the same channel doping, reducing the SRAM area per bit by 39%.
