Picocom is a 5G open RAN baseband semiconductor company with experience in the field of small cells. Its chosen partner, Andes Technology, is a supplier of high-performance, low-power compact 32/64-bit RISC-V CPU cores and the Founding Premier member of the RISC-V International Association.
Picocom is a supporter of 'open RAN' , which involves the disaggregation of 5G radio access networks (RAN), opening up the supply chain and enabling new vendors to enter the market and compete. With Andes performance efficient cores, Picocom’s DU baseband offload SoC will deliver flexibility, efficiency and performance to meet the challenges brought by 5G small cells.
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“Andes N25F 32-bit RISC-V cores are small, yet powerful. Their compact size allows Picocom to use 32 of them, in the form of two clusters, providing flexible processing for data throughputs at line rates up to 25 Gbps for packet header processing,” explained Peter Claydon, President, Picocom. “Our engineering team found that using clusters of small RISC-Vs is more efficient than using a small number of larger cores. This clustered RISC-V approach enables us to retain maximum flexibility to cope with future 5G NR standards changes while delivering excellent performance in a very demanding application.”
“The RISC-V core N25F is a proven outstanding solution for high-speed control tasks and floating-point intensive applications. We are delighted that Picocom recognises the strength of N25F and utilises dozens of them in clusters, along with the integrated Platform AE350 to design its advanced 5G small cell SoC.” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “It again validates that Andes’ RISC-V solutions are ideal to tackle the demanding requirements of high-speed protocol control with significant performance for applications such as storage, networking and wireless communication.”
